AMD begins volume shipments of Spartan UltraScale+ FPGAs

Designed for cost-sensitive edge applications demanding high I/O, low power, and advanced security, AMD’s latest addition to its Cost-Optimized Portfolio brings modern connectivity, post-quantum cryptography, and enhanced features to the proven UltraScale+ platform

AMD has announced that the first devices in its cost-optimized Spartan UltraScale+ family—SU10P, SU25P, and SU35P—have entered volume production and are now available for order. These entry-level FPGAs are supported by the AMD Vivado Design Suite 2025, enabling developers to begin production-level design and deployment. The launch marks a significant milestone in AMD’s ongoing efforts to deliver scalable and affordable FPGA solutions for a wide range of applications.

Built for cost-sensitive edge applications requiring high I/O, low power, and state-of-the-art security features, this new offering in the AMD Cost-Optimized Portfolio brings modernized connectivity, post-quantum cryptography, and more to the proven UltraScale+ portfolio of FPGAs and adaptive SoCs.

First production shipments of the three lowest-density devices mark a significant milestone in the availability of proven, small FPGA solutions for the low and mid-range markets.

A Proven Foundation for Fast Time to Market

Engineers looking for cost-optimized, compact FPGAs also want simplicity and a fast time to market. They need programmable logic, high I/O, robust security, and world-class reliability. They also need tools that deliver push-button timing closure and rapid debug capabilities. Above all, they need a low-risk path to market. Built by the industry leader1 using proven UltraScale+ technology, Spartan UltraScale+ FPGAs deliver exactly that.

With Spartan UltraScale+ FPGAs, AMD starts with a well-established UltraScale+ FPGA fabric, which provides an excellent balance of performance and low power—along with a long product lifecycle. For connectivity, Spartan UltraScale+ FPGAs combine high-density input/output (HDIO) for rich 3.3V I/O support, with new high-speed XP5IO and deliver the industry’s highest ratio of I/O to logic, powered by high-performance and low-power fabric. Designers can also expect fast design convergence and easy reuse across programs with the AMD Vivado Design Suite, offering support for more than 160 AMD FPGAs and adaptive SoCs. In applications such as board control and I/O expansion, where clock speeds rarely exceed 150 MHz, users can expect push-button timing closure for fast design iteration. For applications in machine vision, industrial, and medical requiring higher performance, Spartan UltraScale+ FPGAs deliver a two speed-grade advantage over the competition.

New Capabilities for Cost-Sensitive Applications

Building on this proven foundation, Spartan UltraScale+ FPGAs also bring several new advances to the AMD Cost-Optimized Portfolio:

·       State-of-the-art security with hard IP for post-quantum cryptography using NIST-approved algorithms. This enables both secure device configuration and user access to dedicated cryptographic resources, including a true random number generator (TRNG), physical unclonable function (PUF), secure hashing, and more.

·       An integrated memory controller for LPDDR4X/5 supporting up to 4266 Mb/s on a 32-bit interface saves up to 15 kLC, allowing designers to move into a smaller device and further reduce power and cost.

·       The new XP5IO class supports low-voltage differential signaling (LVDS) up to 1.8 Gb/s, 3.2 Gb/s MIPI D-PHY, and other high-speed differential interfaces.

·       Compliant PCIe Gen4 hard IP, supporting both endpoint and root port applications.

·       Octal SPI interface support for faster configuration and data transfer rates from external flash memory.