Cadence speeds AI chip development with NVIDIA-backed power analysis innovation

This breakthrough enables engineers developing AI, machine learning, and GPU-accelerated systems to analyze power consumption much earlier in the design process, improving energy efficiency and significantly shortening time to market

Cadence Design Systems has announced a major advancement in pre-silicon power analysis, thanks to a deep technology collaboration with NVIDIA. By combining the Cadence Palladium Z3 Enterprise Emulation Platform with the newly developed Dynamic Power Analysis (DPA) App, the two companies have successfully performed hardware-accelerated power analysis of billion-gate AI designs across billions of simulation cycles — all within a few hours and with up to 97% accuracy.

This breakthrough allows designers working on AI, machine learning (ML), and GPU-accelerated technologies to model power consumption far earlier in the design cycle, helping reduce energy use and accelerate time to market.

Solving the power bottleneck in early design

Traditionally, power analysis tools have struggled to scale, often limited to a few hundred thousand simulation cycles due to high compute demands and long runtimes. This limitation made it difficult for semiconductor engineers to predict power consumption under realistic workloads until much later in the development process.

Now, Cadence and NVIDIA’s joint innovation introduces hardware-assisted acceleration and parallel processing techniques that can handle billions of cycles in just two to three hours.

“Cadence and NVIDIA are building on our long history of introducing transformative technologies developed through deep collaboration,” said Dhiraj Goswami, corporate vice president and general manager at Cadence. “This empowers customers to confidently meet aggressive performance and power targets and accelerate their time to silicon.”

Optimizing AI platforms for the future

The Cadence DPA App on the Palladium Z3 platform enables early, accurate modeling of power under real-world conditions. “By combining NVIDIA’s accelerated computing expertise with Cadence’s EDA leadership, we’re advancing hardware-accelerated power profiling to enable more precise efficiency in accelerated computing platforms,” said Narendra Konda, vice president of Hardware Engineering at NVIDIA.

Integrated into Cadence’s end-to-end design flow, the solution helps developers optimize functionality, performance, and energy use long before tapeout. This is particularly critical for AI and GPU-heavy applications, where power efficiency directly impacts cost and scalability.

With this innovation, Cadence and NVIDIA are reshaping the landscape of power modeling, setting a new benchmark for energy-aware chip design in the era of next-generation AI infrastructure.