Synopsys has announced that Fujitsu Semiconductor will be shipping a 2G/3G/4G baseband processor using Synopsys' DesignWare DigRFv4 M-PHY and DigRF 3G PHY IP. Fujitsu Semiconductor has selected Synopsys’ silicon-provenIP to mitigate project schedule risks and help ensure the long-term interoperability of their ASIC design customer's system-on-chip (SoC) with Fujitsu Semiconductor's RFIC products. Integrating DesignWare IP allowed Fujitsu Semiconductor to deliver an efficient, low-power and cost-effective solution.
DaisukeYamazaki, Manager, Design Department, Wireless Solution Division, Fujitsu Semiconductor, said, "Our customer’s next‐generation mobile devices required low‐power, high‐bandwidth connectivity, so we needed a reliable IP solution in the required process technology that was compliant with MIPI standard specifications. Integrating Synopsys’ DesignWare DigRFv4 M‐PHY and DigRF 3G PHY IP helped ensure the successful silicon tape out and production ramp of mobile SoCs targeting 2G/3G/4G speeds with high data rates and low-power consumption."
Synopsys and Fujitsu Semiconductor have worked closely throughout the product development cycle to identify and address differences between the DigRFv4 and DigRF 3G standard specifications, keeping the project schedule on track.
"Synopsys understands the importance of providing companies like Fujitsu Semiconductor with high-quality IP that enables them to reduce integration risk and focus internal resources on other critical parts of the design. Fujitsu Semiconductor’s successful integration of the 28-nanometer DesignWare M-PHY demonstrates our commitment to delivering silicon-proven IP so that our customers can deliver innovative products to the market faster," said John Koeter, Vice- President of Marketing for IP and Systems, Synopsys.
The DesignWare M-PHY supporting multiple protocols, including DigRFv4 and the DigRF 3G PHY, are available for multiple process nodes in the market.
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