Huawei said on Monday that its future high-end chips could achieve transistor density equivalent to 1.4-nanometre process technologies within five years, outlining a new engineering approach designed to bypass constraints created by U.S. semiconductor sanctions.
The announcement, made at a semiconductor symposium in Shanghai, highlights China’s broader push to reduce dependence on Western chipmaking technologies and overcome barriers created by Washington’s restrictions on advanced lithography equipment and semiconductor tools.
The target is notable because 1.4nm-class manufacturing is expected to sit near the global frontier of semiconductor technology by the end of the decade. TSMC, currently the world’s leading advanced chip producer, plans to begin mass production of 1.4nm chips around 2028.
Huawei, however, is attempting to reach similar density levels through a different architectural strategy rather than relying solely on conventional transistor shrinking.
At the center of that effort is what Huawei calls the “Tau Scaling Law,” a new engineering principle designed to improve chip performance by reducing the distance and latency involved in moving data and signals within chips and computing systems.
The approach reflects a growing industry recognition that traditional Moore’s Law scaling is becoming increasingly difficult and expensive even for leading global semiconductor firms.
Rather than depending entirely on smaller transistor geometries, Huawei is focusing on system-level efficiency improvements, including interconnect optimization, shorter wiring paths, and reduced data movement latency.
Huawei said future Kirin chips scheduled for launch later this year will use a related architecture called LogicFolding, which the company says significantly shortens wiring inside chips and improves performance efficiency.
The company also claimed it has already designed and mass-produced 381 chips over the past six years based on Tau Scaling concepts for applications including smartphones and AI computing infrastructure.
The announcement carries broader geopolitical significance because Huawei has become central to China’s domestic AI infrastructure ambitions following U.S. sanctions that severely limited Chinese access to leading-edge semiconductors.
Huawei’s Ascend AI chips are increasingly being used to power Chinese AI models, including recent systems developed by DeepSeek.
Industry analysts say Huawei’s approach reflects a pragmatic shift toward extracting more performance from constrained manufacturing capabilities.
He Hui of Omdia described the strategy as a move from traditional node-based scaling toward system-level efficiency scaling.
That could become increasingly important as global semiconductor progress slows and geopolitical fragmentation reshapes access to advanced manufacturing technologies.
For China, the stakes extend well beyond smartphones or AI accelerators. Advanced semiconductors are now viewed as a core pillar of economic competitiveness, military capability, and technological sovereignty.
Huawei’s roadmap suggests China may increasingly pursue architectural and systems-level innovation to narrow the gap with Western and Taiwanese semiconductor leaders, even if access to cutting-edge fabrication tools remains restricted.
The announcement, made at a semiconductor symposium in Shanghai, highlights China’s broader push to reduce dependence on Western chipmaking technologies and overcome barriers created by Washington’s restrictions on advanced lithography equipment and semiconductor tools.
The target is notable because 1.4nm-class manufacturing is expected to sit near the global frontier of semiconductor technology by the end of the decade. TSMC, currently the world’s leading advanced chip producer, plans to begin mass production of 1.4nm chips around 2028.
Huawei, however, is attempting to reach similar density levels through a different architectural strategy rather than relying solely on conventional transistor shrinking.
At the center of that effort is what Huawei calls the “Tau Scaling Law,” a new engineering principle designed to improve chip performance by reducing the distance and latency involved in moving data and signals within chips and computing systems.
The approach reflects a growing industry recognition that traditional Moore’s Law scaling is becoming increasingly difficult and expensive even for leading global semiconductor firms.
Rather than depending entirely on smaller transistor geometries, Huawei is focusing on system-level efficiency improvements, including interconnect optimization, shorter wiring paths, and reduced data movement latency.
Huawei said future Kirin chips scheduled for launch later this year will use a related architecture called LogicFolding, which the company says significantly shortens wiring inside chips and improves performance efficiency.
The company also claimed it has already designed and mass-produced 381 chips over the past six years based on Tau Scaling concepts for applications including smartphones and AI computing infrastructure.
The announcement carries broader geopolitical significance because Huawei has become central to China’s domestic AI infrastructure ambitions following U.S. sanctions that severely limited Chinese access to leading-edge semiconductors.
Huawei’s Ascend AI chips are increasingly being used to power Chinese AI models, including recent systems developed by DeepSeek.
Industry analysts say Huawei’s approach reflects a pragmatic shift toward extracting more performance from constrained manufacturing capabilities.
He Hui of Omdia described the strategy as a move from traditional node-based scaling toward system-level efficiency scaling.
That could become increasingly important as global semiconductor progress slows and geopolitical fragmentation reshapes access to advanced manufacturing technologies.
For China, the stakes extend well beyond smartphones or AI accelerators. Advanced semiconductors are now viewed as a core pillar of economic competitiveness, military capability, and technological sovereignty.
Huawei’s roadmap suggests China may increasingly pursue architectural and systems-level innovation to narrow the gap with Western and Taiwanese semiconductor leaders, even if access to cutting-edge fabrication tools remains restricted.
