eInfochips launches design services for chips based on 16nm geometry

eInfochips has launched design services for chips based on 16nm geometry. The comprehensive suite of services includes Netlist to GDSII, Sign-off, and Design for Testability.

“Mastering chip design at smaller geometries can only be achieved through hands-on experience. Today, eInfochips is one of the few companies in the world that can say they have experience at 16nm,” said Parag Mehta, Chief Marketing & Business Development Officer, eInfochips.

16nm chips will power a new generation of products that are smaller, require less power and run faster. A recent TSMC report suggests that 16nm FinFET technology will achieve 55% power reduction and 35% higher speed as compared to the standard 28nm HK/MG planar process.

In conjunction with TSMC’s announcement to support volume production at 16nm, eInfochips is taping out 16nm FinFET chips for a leading semiconductor design company. That means the eInfochips design team possessors are hands-on experience using leading EDA Tools across the silicon development cycle. The eInfochips team is also one of the few that have addressed implementation, flow enhancement (including double patterning) and Design Rule Check (DRC) errors at 16nm geometry.