Synopsys has entered into collaboration with United Microelectronics Corporation (UMC) for Pattern Matching-based lithography hotspot checking at the 28-nm process node. IC Validator pattern matching extends the In-Design flow with automatic repair of lithography violations, further optimizing design turnaround time. IC Validator pattern matching also extends the benefits of In-Design physical verification with IC Compiler to eliminate late-stage surprises and manual fixes. This agreement between Synopsis and UMC adds new benefits to In-Design physical verification with IC Compiler for UMC customers.
In-Design physical verification with pattern matching makes it possible for designers to reach and maintain a healthy design earlier, resulting in improved final layout quality and further eliminating accumulation of schedule risk. Pattern matching helps designers to screen for lithography hotspots in a push-button manner, right within the implementation environment.
S. C. Chien, Vice-President, Advanced Technology Development Division, UMC, said, “UMC is constantly implementing the latest design support resources to help our customers streamline their path to silicon success. IC Validator’s pattern-matching technology allows our customers to quickly screen for challenging layout features, eliminating the need for detailed process simulation. Furthermore, using IC Compiler and In-Design technology, this checking is available to IC designers earlier in the design process, helping to mitigate risk throughout the design cycle.”
